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Draw the cache tables and the state of all bits within them. Suppose you have a 16 byte cache with 2 byte long cachelines that is 2-way set associative and write-back. Further assume that prior to processing any read/write requests the state of memory is M[a]-a, or another words, the byte at address 0 is 0, address 1 is 1, address 2 is 2, and so on. Assume an *8 bit long address. Along with depicting the cache tables, please answer the following questions:

a. How many bits are devoted to the line size?
b. How many bits are devoted to the index?
c. How many bits are devoted to the tag?

Answer :

Answer:

Detailed solution is given in attached diagram and the answers are given below:

Explanation:

(a) 4 bits are devoted for line sizing.

(b) 2 bits are devoted for indexing

(c) 1 bit is devoted for the tag

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